The present invention relates to a programmable non-volatile data storage circuit, and in particular, though not limited to an on-chip storage circuit for storing a calibration code for an integrated circuit on the chip. The invention also relates to a method for programming a non-volatile data storage circuit and additionally the invention relates to an integrated circuit comprising a primary circuit and a programmable non-volatile data storage circuit comprising a calibration code for the primary circuit of the Integrated circuit.
It is known to provide an on-chip calibration circuit on an integrated circuit chip for calibrating the integrated circuit For example, in the case of a temperature sensor and its associated integrated circuit the provision of an on-chip calibration circuit permits the storage of a calibration code for calibrating the integrated circuit. Such calibration circuits comprise an array of bi-state bi-stable circuit elements which are selectively addressable for switching from a first to a second state for programming the calibration circuit in general, in their respective first states each circuit element outputs a logic high, and in its second state outputs a logic low, thus permitting the storing of a calibration code in the calibration circuit Such bi-state bi-stable circuit elements may comprise switchable EEPROM cells, but more typically comprise switchable fuses. In a first state each fuse is in its dosed circuit state and is of relatively low impedance. In its second state each fuse is in an open circuit state with relatively high, and preferably, infinite impedance. The fuse of each circuit element is connected to a voltage derived from the supply voltage to the calibration circuit and to ground through a low value constant current sink. An output from each circuit element is provided through a buffer. In the first state the impedance of the fuse is sufficiently low to pull the output of the corresponding circuit element high, thus providing a logic high output. In the second state the impedance of the fuse is sufficiently high to provide a logic low output from the corresponding circuit element.
There are many ways of blowing fuses in selected circuit elements during programming of such a calibration circuit. One such method comprises laser trimming the fuses. The fuses typically are of gate polysilicon, and a laser is used at the wafer sort stage of the manufacture of an integrated circuit to sever the fuses of selected circuit elements. An alternative method for blowing such fuses is to force a large current to flow through the fuses of selected circuit elements, thereby causing the fuses to blow into an open circuit state. An advantage of blowing the fuses by forcing a large current through the fuses is that it permits trimming of the circuit at a later stage of the production process, and in general, this trimming method permits trimming to be carded out at the in-package stage of an integrated circuit chip production process.
However, a disadvantage of trimming by electrically blowing fuses is that additional pins are required to the calibration circuit for facilitating programming thereof. Typically, a power supply pin and a ground pin are required for powering the calibration circuit, a serial data address pin and a serial clock signal pin are required for selecting and addressing the circuit elements to be switched from their respective first to their second states, and an additional pin is, in general, required for receiving an enable signal for enabling the switching of each circuit element when it has been addressed. Thus, the typical number of pins required for programming a calibration circuit is five, and while the power supply and ground pins may be subsequently used for the integrated circuit after programming of the calibration circuit, even allowing for this, three additional pins may be required, one for each of the serial data addresses and the serial dock signal, and usually one for the enable signal. With the ever increasing requirement to minimise the number of pins on an integrated circuit, this method for programming a calibration circuit is becoming unacceptable. There is therefore a need for a programmable non-volatile data storage circuit which minimises the number of pins or terminals required for programming the circuit.
The present invention is directed towards providing such a circuit, and the invention is also directed towards providing a method for programming such a circuit
According to the invention there is provided a programmable non-volatile data storage circuit comprising:
a plurality of selectively addressable first bi-state bi-stable circuit elements, the first circuit elements being electrically switchable from a first state to a second state for programming the storage circuit,
a first terminal for receiving a power supply modulated with one of a serial data input signal with address data of selected ones of the first circuit elements to be switched from the first state to the second state, and a clock signal for clocking the data input signal,
a selectively configurable second terminal for receiving the other of the serial data input signal and the clock signal, and
an interpreter circuit responsive to the data input signal and the clock signal for selecting and addressing each first circuit element to be switched in response to the data input signal, and for enabling switching of each of the selected first circuit elements, and for selectively configuring the second terminal as an input and/or output terminal to operate under the control of a primary circuit with which the data storage circuit is associated, in response to the data input signal.
Preferably, the voltage of the power supply an the first terminal is modulated by the one of the serial data input signal and the dock signal.
Advantageously, the interpreter circuit enables switching of each selected first circuit element when the voltage of the modulated power supply on the first terminal is at a maximum value.
In one embodiment of the invention the interpreter circuit comprises a demodulator for demodulating the modulated voltage of the power supply an the first terminal and for providing the one of the serial data input signal and the clock signal. Preferably, the demodulator comprises a comparator for comparing the voltage of the modulated power supply on the first terminal with a reference voltage, and for outputting the one of the serial data input signal and the clock signal. Advantageously, the reference voltage is selected to lie within the maximum and minimum voltage values of the modulated power supply applied to the comparator. Ideally, the comparator outputs one of a high and low signal in response to the voltage of the modulated power supply applied to the comparator being above the reference voltage, and the comparator outputs the other of the high and low signal in response to the voltage of the modulated power supply applied to the comparator being below the reference voltage.
In one embodiment of the invention the modulated power supply is applied to the comparator through a potential divider.
In another embodiment of the invention the interpreter circuit comprises a state machine for enabling switching of each first circuit element to be switched when the voltage of the modulated power supply is at its maximum value. Preferably, the modulated power supply is applied to each first circuit element when switching of that first circuit element is enabled.
In one embodiment of the invention the interpreter circuit comprises a serial to parallel data interface circuit for converting the serial data input signal to a parallel data signal.
In another embodiment of the invention the first circuit elements are arranged in a matrix comprising a plurality of rows and columns of first circuit elements, and the interpreter circuit comprises an X decoder and a Y decoder for decoding the data signal for selectively addressing each first circuit element by its row and column location, one of the X decoder and the Y decoder being enabled by the state machine for enabling switching of each first circuit element when it is addressed.
Preferably, the second terminal is initially configured as an input terminal for receiving the one of the serial data input signal and the clock signal.
In one embodiment of the invention the second terminal is configurable by the interpreter circuit in response to the data input signal for facilitating reading the status of each first circuit element.
In another embodiment of the invention the second terminal is configurable as an output terminal for outputting a signal from the primary circuit prior to switching of the first circuit elements.
In a still further embodiment of the invention the second terminal is reconfigurable as an input terminal for receiving the one of the serial data input signal and the dock signal until completion of switching of the first circuit elements to be switched in response to the data input signal.
In one embodiment of the invention the second terminal is reconfigurable as an input terminal for receiving the one of the serial data input signal and the clock signal in response to temporary removal of the power supply from the first terminal.
In a further embodiment of the invention the second terminal is configurable by the interpreter circuit to be operable under the control of the primary circuit in response to switching of the first circuit elements to be switched being completed.
In a further embodiment of the invention a second bi-state bi-stable circuit element is provided, the second circuit element being electrically switchable from a first state to a second state for preventing further switching of the first circuit elements, the second circuit element being selectable and addressable by the interpreter circuit in response to the data input signal for switching from the first state to the second state. Preferably, the second circuit element comprises a blowable fuse having a relatively low impedance in a conducting state corresponding to the first state, and a relatively high impedance in a non-conducting state when blown into an open circuit state corresponding to the second state. Advantageously, an addressable switch is provided in the second circuit element, the switch being selectively addressable and being enabled by the interpreter circuit in response to the data input signal for applying the power supply to the fuse for blowing thereof. Ideally, the interpreter circuit is non-responsive to modulation of the power supply on the first terminal after the second circuit element has been switched from the first state to the second state.
In one embodiment of the invention the second circuit element is irreversibly electrically switchable from the first state to the second state.
In another embodiment of the invention each first circuit element comprises a blowable fuse having a relatively low impedance in a conducting state corresponding to the first state, and a relatively high impedance in a non-conducting state when blown into an open circuit state corresponding to the second state.
In one embodiment of the invention an addressable switch is provided in each first circuit element the switch of each first circuit element being selectively addressable and being enabled by the interpreter circuit in response to the data input signal for applying the power supply to the fuse for blowing thereof.
In another embodiment of the invention each first circuit element is irreversibly electrically switchable from the first state to the second state.
In a further embodiment of the invention the first circuit elements are sequentially selectable for switching by the interpreter circuit.
In one embodiment of the invention the first terminal is adapted for receiving the power supply modulated with the serial data input signal, and the second terminal is adapted for receiving the clock signal for clocking the data input signal to the interpreter circuit.
The invention also provides an integrated circuit comprising a primary circuit, and the programmable non-volatile data storage circuit according to the invention for storing a calibration code for the primary circuit, the first terminal providing the power supply to the primary circuit, and the second terminal being selectively configurable to be operable under the control of the primary circuit in response to the data input signal.
Additionally, the invention provides a method for programming a non-volatile data storage circuit comprising a plurality of selectively addressable first bi-state bi-stable circuit elements, the first circuit elements being electrically switchable from a first state to a second state for programming the data storage circuit, the method comprising the steps of:
applying a power supply to the data storage circuit through a first terminal thereof, and modulating the power supply with one of a serial data input signal with address data of selected ones of the first circuit elements to be switched from the first state to the second state, and a dock signal for docking the data input signal,
applying the other of the serial data input signal and the clock signal to a selectively configurable second terminal thereof,
reading the data input signal,
selecting and addressing each circuit element to be switched in response to the data input signal and enabling switching of each selected circuit element, and selectively configuring the second terminal in response to the data input signal as an input and/or output terminal to operate under the control of a primary circuit with which the data storage circuit is associated.
Preferably, the voltage of the power supply on the first terminal is modulated by the one of the serial data input signal and the clock signal.
Advantageously, switching of each selected first circuit element is enabled when the voltage of the modulated power supply on the first terminal is at a maximum value. Ideally, the voltage of the power supply on the first terminal is demodulated for providing the one of the serial data input signal and the clock signal.
In one embodiment of the invention the power supply on the first terminal is modulated with the serial data input signal, and the dock signal is applied to the second terminal.
Further the invention provides a method for operating an integrated circuit comprising a primary circuit, and the programmable non-volatile data storage circuit according to the invention for storing a calibration code for the primary circuit, the method comprising the steps of calibrating the primary circuit by storing a calibration code in the data storage circuit, the calibration code being stored in the data storage circuit by modulating the power supply to the first terminal with one of a serial data input signal with address data of selective ones of the first circuit elements to be switched from the first state to the second state in order to store the calibration code, and a clock signal for docking the data input signal, and applying the other of the serial data input signal and the dock signal to the second terminal of the data storage circuit reading the data input signal, selecting and addressing the first circuit elements to be switched from the first state to the second state and enabling switching of the addressed first circuit elements, configuring the second terminal in response to the data input signal as an input and/or output terminal operable under the control of the primary circuit and powering the primary circuit through the first terminal.
Preferably, the second terminal is configured as an input and/or output terminal operable under the control of the primary circuit in response to storage of the calibration code in the data storage circuit having been completed.
The advantages of the invention are many. The principal advantage of the invention is that it provides a programmable non-volatile data storage circuit in which the number of terminals required to address the circuit is minimised. Only three terminals are required for powering and programming the circuit, namely, the first terminal, which is the power supply terminal for powering the data storage circuit and through which either the address data in the form of a serial digital data input signal or the clock signal is inputted by modulating the power supply, a second terminal for receiving the other of the serial data input signal and the dock signal, and a ground terminal. A particularly advantageous construction of the data storage circuit is provided when the power supply on the first terminal is modulated with the serial data input signal, and the clock signal is applied to the second terminal. In particular, the programmable non-volatile data storage circuit is ideally suited for storing a calibration code for calibrating an integrated circuit, and when used in conjunction with such an integrated circuit for calibrating the integrated circuit, no additional terminals are required, since the first terminal used for powering and addressing the data storage circuit during programming can subsequently be used as a power supply terminal for the integrated circuit, and the second terminal can be subsequently used as an input and/or output terminal from the integrated circuit The ground terminal is a common terminal.
The invention will be more dearly understood from the following description of a preferred embodiment thereof, which is given by way of example only, with reference to the accompanying drawings.